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Physical Design Training

Physical design training is a 7 months course with hands on exposure to both Synopsys and Cadence Innovus tools covering all the aspects starting from digital design basics to advanced physical design using multiple hands on projects at 14nm.

📆Duration: 7 Months
🌐Mode: Online Live Sessions with Recorded Access
🧰Tools Covered: Synopsys and Cadence Innovus  Tools.

Overview of the course

Industry-Aligned Training in VLSI Backend Flow with Hands-On Tools and Projects

The Physical Design Training program at Vidyouth Intelligence is a 7-month, career-focused course designed to provide in-depth knowledge of the complete VLSI backend flow—from Netlist to GDSII. The program begins with core fundamentals such as device physics, IC fabrication, timing concepts, and advanced digital design, and progresses to detailed implementation practices using industry-grade EDA tools.

What You Will Learn:

  • Foundational Concepts: Semiconductor device fundamentals, CMOS technology, fabrication techniques, timing analysis, and advanced digital logic design.

  • Complete Backend Flow: Step-by-step understanding of Floorplanning, Placement, Power Planning, Clock Tree Synthesis, Routing, Timing Closure, and Engineering Change Orders (ECOs).

  • Operating System and Scripting Skills: Practical knowledge of Linux OS and scripting with TCL to enable effective automation and tool handling.

  • Tool Expertise: Practical exposure to industry-standard tools such as Synopsys DC, ICC II, StarRC, PT, and Cadence Innovus Implementation System.

  • Project-Based Learning: Implementation of both block-level and full-chip physical design projects guided by experienced trainers.

Key Features:

  • Carefully structured syllabus aligned with current industry demands.

  • More than 40 assignments covering all aspects of physical design implementation, each integrated into course lectures.

  • Strong emphasis on real-time examples and case studies drawn directly from industry practices.

  • Balanced approach between comprehensive theory sessions and lab sessions to ensure applied understanding.

  • Continuous mentoring, regular evaluations, and problem-solving support throughout the course.

Why Vidyouth Intelligence:

  • Designed and delivered by VLSI professionals with deep industry experience.

  • Hybrid learning model: theory sessions delivered online and lab sessions conducted offline for practical exposure.

  • Personalized support, one-on-one guidance, and focused placement assistance.

  • Affordable training with proven outcomes for students pursuing core VLSI roles.

The Physical Design Training at Vidyouth Intelligence ensures that students are well-prepared to enter the semiconductor industry with confidence, practical skills, and project experience.

Course Syllabus

VLSI Design flow
Semiconductor device fundamentals
IC fabrication
  • Layers of CMOS
  • Depositing oxide layer
  • Photolithography
  • Masking
  • Etching Layers
  • Formation of nwell
  • Self aligned gate fabrication process
  • Diffusion to create n+ and P+ regions
  • Metallization
Advanced Digital Design
  • Combinational logic
    • Number systems
    • Radix conversions
    • K-maps, min-terms, max terms
    • Logic gates
    • Realization of logic gates using mux’s and universal gates
    • Compliments (1/2/9/10’s complement)
    • Arithmetic operations using compliments
    • Boolean expression minimization, Dmorgan theorems
    • POS and SOP
    • Conversion and realization
    • Adders
      • Half adder
      • Full adder
    • Subtractor
      • Half subtractor
      • Full subtractor
    • Multiplexers
    • Realizing bigger Mux’s using smaller Mux’s
    • Implementing Adders and subtractors using Multiplexers
    • Decoders and Encoders
    • Implementing Decoders and Encoders using Mux and Demux
    • Bigger Decoder/Encoder using smaller Decoder/Encoder
    • Comparators
    • Implementing multi bit Comparators using 1-bit Comparator
  • Sequential logic
    • Latch, Flipflop
    • Latch, Flipflop using Gates or Mux’s
    • Different types of FFs
    • FF Truth table
    • Excitation tables
    • Realization of FF’s using other FF’s
    • Applications of FF’s, Latches
      • Counters
      • Shift registers
      • Synchronizers for clock domain crossing
      • FSM’s
      • Mealy, Moore FSM
      • Different encoding styles
      • Frequency dividers
      • Frequency multiplication
    • STA
      • Setup time, Hold time, timing closure
      • fixing setup time and hold time violations
      • Launch flop, capture flop
PD flow keywords and VSLI Technology concepts
  • Introduction to majorly used keywords on PD flow
  • VLSI Technology concepts
    • Resistance, Capacitance, Inductance
    • Parasitic capacitance
    • L-C-R circuit analysis
    • RC circuit significance with circuit delay
  • Clock distribution concepts, skew
Linux commands – hands on training
  • Installing Linux platform in Windows
  • Linux basics
  • Linux versus Windows
  • Linux Terminal
  • File and Directory management
  • Changing file permissions
  • Absolute path and relative path
  • Working with directories
  • GVIM – major keyboard shortcuts
  • Text display commands
  • Root configuration files
  • Environment variables
  • Text processing commands
    • grep, fgrep
    • xargs
    • SEd
    • AWK
    • Pipes and filters
  • Connecting to server
  • Process management
  • LSF
  • Ping
  • FTP
  • CTAGs
  • File compress and extract
  • Soft links
TCL Scripting
  • Overview
  • Env Setup
  • Special Variables
  • Data Types
  • Variables
  • Operators
  • Decisions
  • Loops
  • Arrays, Strings, Lists, Dictionary
  • History and Redoing of commands
  • String Pattern Matching commands
Synthesis
  • Basics of Synthesis
  • High Level Synthesis Flow
  • Reading of Verilog RTL File
  • Target and Link Libraries
  • Resolving References with Link Libraries
  • Reading hierarchical Designs
  • Reading ddc design
  • Analyse & Elaborate Commands
  • Constraining and Compiling RTL
  • Post Synthesis Output Data
Timing Constraints
  • Constraining Register to Register Paths
  • Constraining Inputs Paths
  • Constraining Outputs Paths
  • Virtual Clock
  • Load Budgeting
  • Default Path Groups
  • Creating User-defined Path Groups
  • Prioritizing Path Groups
  • Timing Reports
  • Analyzing Timing Reports
  • Defining a Clock with additional options
  • Input Delay with additional options
  • Output Delay with additional options
  • Pre-CTS versus Post CTS Clock Latencies
  • Independent IO Latencies
  • Output Delay with Network Latency
  • Output Delay with Source Latency
  • Different IO versus Internal Latencies
  • IO Clock Latencies
  • Handling Different IO Vs Internal Latencies
  • Virtual External Clock Latencies
  • Included External Clock Latencies
  • Multiple Synchronous Clocks
  • Multiple Clocks Input Delay
  • Maximum Internal Input Delay
  • Multiple Clock Output Delay
  • Maximum Internal Output Delay
  • Inter Clock Uncertainty
  • Generated Clocks
  • Mutual Exclusive Synchronous Clocks
  • Logically Exclusive Clocks
  • Multiple Clocks per Register
  • Cross Talk Analysis
  • Asynchronous Clocks
  • Multi Cycle Paths and Constraints
UPF
  • High Level Multi-Voltage Design Concepts
  • Supplies and Power Domains
  • Power Ports and Nets
  • Level Shifters
  • Power States and PS Table
NDM Labraries
  • IC Compiler II Library Manager
  • ICC Compiler II NDM Cell Library
  • Cell Library Characteristics
  • Library Manager Flow
  • Tech Only NDM Library
  • Technology-Only Library Flow
  • Technology File
  • Read TLU+ Files
  • Tech Library Preparation
Initial Design Setup
  • Top Level, Sub-System Level and Block Level Design Setup
  • Set up initial Design Implementation
  • Loading Netlist from Synthesis
  • Setting Path to dotlibs, LEFs, DEFs (if needed), Technology Files, SDC files
  • Flow Setup and Design Setup
  • Loop-back to Synthesis for Correlation issues correction
Placement
  • Running placement
  • Defining placement strategies
  • In Place Optimization
  • Hierarchical Placement
  • Relative Placement
  • Congestion analysis and reduction
  • Macro placement changes to reduce congestion
  • Standard Cell Placement Constraints
  • Halo creation for instances
  • Congestion Analysis with Standard Cell placement
  • Local Congestion Reduction
  • Density Screen and Placement Blockage for Standard Cells
  • Congestion Aware Placement
  • Re-Check Macro Placement for better Congestion relief
  • Create Balanced Buffer Trees for High Fanout Net
Power Planning
  • Defining Power Structure
  • Logical Power/Ground Connections
  • Setting Power Network Constraints
  • Create and Analyze Power Structure
  • Change Power Constraints and Re-Createto meet IR requirements
  • Power Ground Pin connection and create Power Rails
  • Power Network Checks for IR and Resistance
  • Placement Blockage for Power Network
  • Incremental Placement
Scan Chain RE-Ordering and RE-Partitioning
  • Re-Order Scan connectivity within Chain
  • Re-Partition Scan connectivity across Chains
  • SCANDEF file based Scan Chain Re-Ordering
Floor Planning
  • Initial Floorplanning settings
  • Define Pad Instances (Physical Cells)
  • Pad Instance co-ordinates
  • Start Floorplaning
  • Core Die Size setting
  • Floorplanning of Pad Instances
  • Pad Filler Insertion
  • Define Pad Ring Power Grid
  • Macro Instance constraints
  • Macro Instance Array creation
  • Macro Instance Orientation
  • Anchor based and Relative Placement of Macro Instances
  • Macro Instance-Channel settings
  • Macro Instance placement – Manual
  • Congestion probability around Macro Instances
  • Defining Placement Blockages
Global Routing
  • Congestion checks for Overflow again
  • RC extraction for Net Parasitics
  • Check Timing for Max Analysis
  • Run Timing/Congestion aware Placement
  • Logic Re-Structuring for Placement and Timing
Clock Tree Synthesis
  • Check Pre-CTS timing based on Global Routing and Detailed Placement
  • Setting Clock Constraints such as Target Skew Target Insertion Delay
  • Clock Root Attributes as Stop, Float and Exclude Pins
  • Building for Generated and Gated Clocks
  • Don’t Touch attribute on existing Clock Tree structure
  • Defining Clock Buffers and Inverters.
  • Set Clock Tree Timing DRCs.
  • Non-Default Clock Routing rules setting
  • Perform Clock Tree Synthesis and Clock Tree Optimization
  • Reduce Hold Violations in Data paths and Scan Paths
  • Clock Tree Building/Optimization for Multiple modes and Multiple PVT corners
  • Synchronous Clock Balancing
  • Cross-Clock Delay Balancing
  • Logical Hierarchy aware CTS
  • Max and Min Analysis and subsequent Optimization
  • Fixing Violations
  • CTS Optimization across other modes and PVT corners (MMMC)
  • Skew and Insertion Delay checks
  • Checking Crosstalk on Clock Network
Detailed Routing
  • Pre-Route check points
  • Routing fundamentals
  • Global Route
  • Detail Routing
  • Track Assignment and Route
  • Refining Detailed Route
  • Over the Macro routing
  • Non-Preferred Routing direction
  • Clock Net Routing
  • Initial Data path routing
  • Redundant VIA insertion setting
  • Post Detailed Route Optimization
  • Fixing DRC Violations
  • Post Detailed Route Delay Calculation Algorithms
  • Crosstalk Delay and Noise Analysis and Fix
Power Analysis (Static and Dynamic)
  • Check Leakage Power Dissipation
  • VT Cell swap for power and timing trade-off
  • Analyzing Dynamic Power Dissipation based on GAF, SAIF, VCD
  • Reduce Dynamic power
  • Meet Total Power target
Engineering Change Order Flow (ECO)
  • Functional ECO
  • Timing ECO
  • Metal Only ECO using Spare Cells for base frozen designs
Multiple Industry standard Projects
  • Projects covering detailed flow from Input files, floorplan, power planning, placement, CTS, Routing, SPEF extraction, STA, and Physical verification.
    • One project completely guided by the trainer
    • Other project done by student with trainer guidance
  • Project based on multi voltage domain.
Design For Manufacturability
  • Antenna Rules and Fixes
  • Critical Area Analysis
  • Wire Spreading and widening
  • Setting minimum metal jog length
  • Filler Cell Insertion
  • Metal Fill
  • Timing Checks after Metal Fill
  • Parasitic Extraction for SignOff timing analysis
  • Export Netlist
  • Export GDSII
Softskill Training
  • Facing interviews effectively
  • Industry work culture
  • Group discussions

Course Highlights

  • 100% Placement Support
  • Designed for Freshers
  • System Verilog, UVM, Protocols
  • Trainers from MNCs with 10+ Years’ Experience
  • Daily Class Recordings
  • 24×7 Support
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