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DFT TRAINING

DFT Training is a 7-month course providing in-depth exposure of multiple DFT techniques including Scan, ATPG, JAG, and MBIST, with hands-on exposure to Mentor Graphics Tessent and Synopsys TetraMax tools. This course covers complete DFT flow starting from RTL and gate-level netlist, scan insertion, test point insertion and test compression with multiple hands-on projects.

📆Duration: 7 Months
🌐Mode: Online Live Sessions with Recorded Access
🧰Tools Covered: Synopsys TetraMax tools, MentorGraphics Tessent 

Overview of the course

Comprehensive DFT Training with Industry-Standard Tools, Techniques & Projects
The DFT Training Program at Vidyouth Intelligence is a career-focused, hands-on course designed to equip students with essential skills in Design for Testability. The course covers all major DFT techniques including SCAN, ATPG, JTAG, MBIST, and test compression using industry tools and real-time project work.

What You Will Learn

DFT Foundations
Understand testability basics, fault models like stuck-at, transition delay, path delay, and SOC scan architecture.

Advanced DFT Techniques
Learn Scan Insertion, ATPG generation, JTAG control, Test Compression, Boundary Scan, MBIST, and Logic BIST methods.

Tool Proficiency
Work extensively with MentorGraphics Tessent – the industry’s leading DFT tool used by over 80% of semiconductor companies.

Project-Based Learning
Execute hands-on projects involving scan design, test pattern creation, JTAG integration, and memory testing using real-world examples.

Key Features
Structured curriculum aligned with DFT flows used in top VLSI companies
Multiple projects covering scan, compression, ATPG, and MBIST
12-month access to Tessent tools with optional extension
Interactive sessions, regular assignments, and personalized guidance

Why Vidyouth Intelligence
Training led by industry professionals with deep DFT expertise
Emphasis on both fundamental understanding and real-time application
Hybrid learning format combining online theory and offline lab practice
Tailored for freshers and professionals aiming to specialize in VLSI test engineering

The DFT Training Program ensures that students are job-ready with the testability knowledge and hands-on experience required in the semiconductor industry.

Course Syllabus

VLSI Design flow
  • Specification
  • RTL coding, lint checks
  • RTL integration
  • Connectivity checks
  • Functional Verification
  • Synthesis & STA
  • Gate level simulations
  • Power aware simulations
  • Placement and Routing
  • DFT
  • Custom layout
  • Post silicon validation
Digital Design - Deep dive
  • Combinational logic
    • Number systems
    • Radix conversions
    • K-maps, min-terms, max terms
    • Logic gates
    • Realization of logic gates using mux’s and universal gates
    • Compliments (1/2/9/10’s complement)
    • Arithmetic operations using compliments
    • Boolean expression minimization, Dmorgan theorems
    • POS and SOP
    • Conversion and realization
    • Adders
      • Half adder
      • Full adder
    • Subtractor
      • Half subtractor
      • Full subtractor
    • Multiplexers
    • Realizing bigger Mux’s using smaller Mux’s
    • Implementing Adders and subtractors using Multiplexers
    • Decoders and Encoders
    • Implementing Decoders and Encoders using Mux and Demux
    • Bigger Decoder/Encoder using smaller Decoder/Encoder
    • Comparators
    • Implementing multi bit Comparators using 1-bit Comparator
  • Sequential logic
    • Latch, Flipflop
    • Latch, Flipflop using Gates or Mux’s
    • Different types of FFs
    • FF Truth table
    • Excitation tables
    • Realization of FF’s using other FF’s
    • Applications of FF’s, Latches
      • Counters
      • Shift registers
      • Synchronizers for clock domain crossing
      • FSM’s
      • Mealy, Moore FSM
      • Different encoding styles
      • Frequency dividers
      • Frequency multiplication
    • STA
      • Setup time, Hold time, timing closure
      • fixing setup time and hold time violations
      • Launch flop, capture flop
Linux operating system
  • Installing Linux platform in Windows
  • Linux basics
  • Linux versus Windows
  • Linux Terminal
  • File and Directory management
  • Changing file permissions
  • Absolute path and relative path
  • Working with directories
  • GVIM – major keyboard shortcuts
  • Text display commands
  • Root configuration files
  • Environment variables
  • Text processing commands
    • grep, fgrep
    • xargs
    • SEd
    • AWK
    • Pipes and filters
  • Connecting to server
  • Process management
  • LSF
  • Ping
  • FTP
  • CTAGs
  • File compress and extract
  • Soft links
TCL Scripting
  • Introduce TCL
  • Why TCL?
  • TCL Script Processing
  • Understand TCL uses and strengths
  • Writing simple TCL scripts
  • TCL for VLSI scripting
  • TCL : Main Features
  • TCL in EDA
  • TCL shell (tclsh)
  • Working with TCL scripts (UNIX)
  • TCL Interpreter in SoC Design Tools
  • TCL Scripting for SoC Design
  • TCL Commands
  • Variables
  • Substitution and Command Evaluation
  • Operators
  • Mathematical Functions
  • Procedures
  • Control flow : if, if-else, switch, for, foreach, while, break and continue
  • string, string operations
  • List, List manipulation
  • Arrays, array methods
  • Working with files
  • Command line arguments
  • Regular expressions
  • Complete TCL Scripts
  • TCL Packages
Verilog basics
  • Verilog language constructs
  • Combinational logic implementation using Verilog
  • Testbench coding for combinational logic
  • Sequential logic implementation using Verilog
  • Testbench coding for sequential logic
  • Clock generation with frequency , Jitter and duty cycle
  • Memory coding and test bench setup
  • Running simulations, analysing waveforms, debugging concepts
Design For Testability (Below is DFT Main course weekly schedule)
  • DFT Basics
  • SoC Scan architecture overview
  • Types of Scan
  • ATPG DRC Debug
  • ATPG Simulation Mismatch Debug
  • DFT Diagnosis
  • JTAG
  • MemoryBIST
  • LogicBIST
  • Scan and ATPG
  • Test compression technigues
  • Hierarchical Scan Design
Week one
  • Introduction to DFT
  • Roles in DFT
  • Full SOC flow – DFT
  • DFT Architecture and Basics
  • Test Plan
  • Different DFT schemes
  • Comparison between Functional and DFT Vectors
  • Defect, Fault and Error
  • Revision of Digital Concepts
Week two
  • Understanding of SCAN Insertion
  • Scan methodology
  • Types of Scan
  • Top-down and Bottom-up Approach
  • Scan insertion Flow
  • Scan operation
  • Clocking structure relation in SCAN
  • DFT rule checks – Clock and Reset
Week three
  • Scan insertion Scripts
  • Multiple Clock domains
  • DFT Rule Checks – Advanced (Tristate, PRC, XS)
  • Precautions for building a proper scan chain
  • Edge and Domain Mixing significance
  • Scan Configurations
  • Scan chain Balancing
  • Lock up and Terminal lockup latches
  • Hands-on Scan insertion
  • Explanation about Netlist and Library files
  • Assignments
Week Four
  • Hook-Up Scan sub chains
  • Introduction to compression
  • Compression Architecture
  • Decompressor and Compactor
  • LFSR
  • Compression Ratio
  • Masking Logic
  • One hot Decoder
  • Internal scan chains
  • DRC Analysis
  • Scan Reorder
  • Control signals
Week five
  • Modular Compression
  • Introduction to Synthesis
  • Hands-on Compression
  • Assignments
  • ATPG Tools Introduction
  • Fault Models
  • Fault Categories
  • Algorithms used in ATPG
Week six
  • ATPG Flow
  • Coverage Analysis
  • Fault Classes
  • ATPG DRC’s
  • Hands-on Stuck-at ATPG
  • Assignments
Week seven
  • Concepts related to STA – Basics
  • MCP and FP
  • Reports of ATPG
  • Sequential Depth
  • Transition delay faults (TDF)
  • Path delay faults (PDF)
  • Hands-on TDF ATPG
Week Eight
  • Types of patterns
  • Formats of patterns
  • Fault grading
  • LOC , LOS and LOES
  • On chip clock control
    • Advantages
    • Dis-advantages
    • Internal structure
Week nine
  • Introduction to Validation
  • Simulations flow
  • Tools for simulation
  • Simulation mismatches debug
  • No timing and Timing based Simulations
  • Hands-on Simulations
Week ten
  • Flat Models
  • Introduction to JTAG/IJTAG
  • Introductions to PADS
  • BS Insertion
  • JTAG/IJTAG FSM
  • Instructions of JTAG/IJTAG
Week eleven
  • Introduction to MBIST
  • Memory faults
  • Memory grouping
  • Memory basics
  • Algorithms
    • Zero-one, CHBK , MATS .MARCH ,SMARCH ..etc
  • MBIST Insertion on RTL
  • Hands on BIST insertion
  • Assignments
Week twelve
  • Discussion of Interview questions
  • Compactor explanation
  • Memory pipelining
  • ET flow
  • Hierarchical BIST insertion
  • Hands of multi core MBIST insertion
  • Assignments
Week thirteen
  • Complete Flow of BIST insertion and validation
  • Clock Monitoring
  • ICL network
  • EDT and OCC insertion on RTL
  • Gray box generation
  • Assignments
Week fourteen
  • Introduction to ICL and PDL
  • Scan Wrapper insertion – Hierarchical Flow
  • Intest and Extest Hands on Lab sessions
  • Assignments
  • ATPG Flow with TSDB
  • Faults merging
Week fifteen
  • Controlling PLL and CLK Gen’s using ICL and PDL
  • Introduction to BISR
  • Auxiliary Pins
  • Revision of JTAG/IJTAG and BIST concepts
Week sixteen
  • Support for Mock interviews
  • Interactive sessions
  • Complete Revision of DFT as follows:
    • DFT Overview
    • SCAN
    • COMPRESSION
    • OCC
    • JTAG/IJTAG
    • MBIST/MBISR
    • ATPG
    • SIMULATIONS – ATPG and BIST
    • Handling third party IP’s for DFT
    • DFT Insertions in both RTL and NETLIST
  • Total 4 levels of Projects in the entire course duration. Each Level contains 5-10 Working Labs.

Course Highlights

  • 100% Placement Support 
  • Designed for Freshers
  • System Verilog, UVM, Protocols
  • Trainers from MNCs with 10+ Years’ Experience
  • Daily Class Recordings
  • 24×7 Support
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