• Combinational logic
• Number systems
• Radix conversions
• K-maps, min-terms, max terms
• Logic gates
• Realization of logic gates using mux’s and universal gates
• Compliments (1/2/9/10’s complement)
• Arithmetic operations using compliments
• Boolean expression minimization, Dmorgan theorems
• POS and SOP
• Conversion and realization
• Adders
• Half adder
• Full adder
• Subtractor
• Half subtractor
• Full subtractor
• Multiplexers
• Realizing bigger Mux’s using smaller Mux’s
• Implementing Adders and subtractors using Multiplexers
• Decoders and Encoders
• Implementing Decoders and Encoders using Mux and Demux
• Bigger Decoder/Encoder using smaller Decoder/Encoder
• Comparators
• Implementing multi bit Comparators using 1-bit Comparator
• Sequential logic
• Latch, Flipflop
• Latch, Flipflop using Gates or Mux’s
• Different types of FFs
• FF Truth table
• Excitation tables
• Realization of FF’s using other FF’s
• Applications of FF’s, Latches
• Counters
• Shift registers
• Synchronizers for clock domain crossing
• FSM’s
• Mealy, Moore FSM
• Different encoding styles
• Frequency dividers
• Frequency multiplication
• STA
• Setup time, Hold time, timing closure
• fixing setup time and hold time violations
• Launch flop, capture flop

• Unix Operating System
• Kernel
• Unix Shells, RC files
• Shell scripting basics (as required for job)
• Unix Directory structure, hard/soft links
• Xterm, Xhost, commonly used commands
• Text editors
• Revision Management
• Makefile, Cronjob
• Mapping Unix directories, file with Gvim editor
• FTP, SCP, Mail, Compress, sleep, regular expressions
• LSF, Batch submission, Process monitoring
• Revision Management with hands on labs

• Basic Passive and Active devices.
• Ohms law, Kirchoff laws
• Basic of circuit understanding

Transistors in Hardware Design
Significance of transistors in hardware design
Logic gate implementation using BJT and CMOS

Semiconductors
What makes a semiconductor a special element
Classification of solids: conductor, insulator, semiconductor
Energy bands in solids

Types of Semiconductors
Intrinsic semiconductors
Extrinsic semiconductors
N-type extrinsic semiconductor
P-type extrinsic semiconductor
Si vs Ge comparison
Types of current in semiconductors – drift and diffusion

PN Junction Diode
PN junction diode operation in forward and reverse bias
V-I characteristics of PN junction diode
Different types of diodes
Applications of diodes

Bipolar Junction Transistor (BJT)
What is a BJT
Working principle of BJT
BJT fabrication steps
Types of BJT
How BJT is used in large scale manufacturing
Why BJT is not used in lower technology nodes
Issues with BJT
Advantages of BJT
NAND gate implementation using BJT

Field Effect Transistor (FET)
What is a field effect transistor
Types of FET: NMOS, PMOS, CMOS, FinFET

NMOS Transistor
What is NMOS
NMOS working principle
Different voltages, currents, and their equations
NMOS circuit representation
How NMOS works like a switch
NMOS fabrication steps
Types of NMOS
How NMOS is used in large scale manufacturing
Why CMOS is used instead of NMOS
Issues with NMOS
Advantages of NMOS
NAND gate implementation using NMOS

CMOS Technology
What is CMOS
CMOS working principle
Different voltages, currents, and their equations
CMOS circuit representation
How CMOS works like a switch
CMOS fabrication steps
Types of CMOS
How CMOS is used in large scale manufacturing
Issues with CMOS
Advantages of CMOS
NAND gate implementation using CMOS
CMOS second-order effects

FinFET Technology
What is FinFET
FinFET working principle
Different voltages, currents, and their equations
FinFET circuit representation
How FinFET works like a switch
FinFET fabrication steps
Types of FinFET
How FinFET is used in large scale manufacturing
Issues with FinFET
Advantages of FinFET
NAND gate implementation using FinFE

• Layers of CMOS
• Depositing oxide layer
• Photholithography
• Masking
• Ethching Layers
• Formation of nwell
• Self aligned gate fabrication process
• Diffusion to create n+ and P+ regions
• Metallization

• Overview
• Env Setup
• Special Variables
• Data Types
• Variables
• Operators
• Decisions
• Loops
• Arrays, Strings, Lists, Dictionary
• History and Redoing of commands
• String Pattern Matching commands

• Layout Editor Tool
• Understanding the schematic symbols and parameters
• Creating and managing libraries and cell
• Commands for Layout editing.
• Commands for schematic editing.
• Verification : DRC and LVS
• Antenna effect, latchup, Electromigration, IR Drop
• Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
• Resistor, Capacitor layout techniques
• CMOS and BiCMOS layout techniques
• Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop

• Schematic entry
  • Early parasitics
    • Estimated parasitic assistant
  • Reliability analysis
    • Static circuit checks(CCK)
• Pre-layout simulation and analysis
  • Standard cells
  • Analog circuits
  • Analog and mixed mode circuits
• Layout
  • Analog and Digital co-design
    • Fusion compiler co-design
    • IC Compiler II co-design
    • IC Compiler co-design
  • In-design error checks
    • DRD
    • IC Validator live DRC
    • Via checks
    • Metal Density analysis
    • Color decomposition
  • In-design electrical checks
    • Electro migration
    • Resistance
    • Capacitance
    • Shield coverage
    • Voltage annotation for VDRC
  • Early parasitics
    • Estimated parasitic assistance
    • Partial layout extraction
  • Power device design
    • Power device designing
  • Analog design migration
    • Schematic migration
    • Layout migration 

• Mismatches and Matching
  • Techniques
    • Inter digitization
    • Common centroid
• Failure Mechanism
  • Electro migration
  • IR drop
  • LOD & Stress effects
  • WPE, Antenna Effects
  • Latch up
  • ESD
    • High voltage rules
    • EOS effects
• Noises & Coupling
• Different Types of process
  • Advantages & Disadvantages of below
  • Planar CMOS
  • FD-SOI
  • SOI
  • Bi-CMOS
  • Gallium Arsenide
  • Silicon-Germanium
  • Finfet
• Full Chip Construction
  • Scribe Seal
  • Pad Frame
  • Integration and guidelines
• Packaging

• Std Cell & Memories.
• IO Layout Guidelines : High speed IOs and High Speed Interfaces.
• Sense amplifier & Bit cell development
• Why memory layout different than analog layout
• Memory layout flow
• Types of memory layout (SRAM/DRAM/ROM)
• Introduction to SRAM memory layout
• Fixing few manually created leaf-cell errors which impact
• Abutment issues
• Impact of IR, EM and DFM .
• SRAM memory design architecture
• Words line and address line
• SRAM rows and column design
• Building blocks of SRAM
• Memory Bit cell
• Row decoder
• Word line driver
• Sense amplifier
• Control block
• Misc digital logic.
• Pitch Calculation for blocks.
• Power Planning

• High speed Analog Layout
• RF Layout guidelines with Transmission lines and inductor concepts
• Handling clocks
• Analog Circuits & Layout guidelines
• Single & Multi stage differential opamp layout
• current mirror layout
• PLL, DLL and Oscillators
• LDO and other regulators
• ADCs & DACs
• Bandgap, Temperature sensors & Biases -> Current & Voltage bias lines
• Large drivers
• input pair, differential routing, Power routing, offset minimising
• Power/Signal IR Drop
• cross-talk and coupling
• Electrostatic Discharge
• Deep Sub-micron Layout Issues
• Shallow Trench Isolation (LOD)
• Well Proximity Effect

• Design Rule Checks
• Layout Versus Schematic (LVS)
• Electrical Rule Checks (ERC)
• Antenna Checks
• Latch-up
• Reliability checks like EM and IR analysis
• Design for manufacturability (DFM)checks
• Electrostatic discharge (ESD) path checks

• Assignments and multiple hands on projects
• Best Practices & Interview Questions.