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RTL DESIGN AND INTEGRATION COURSE

RTL Design and Integration training is a 3.5 months course focused on all the aspects of RTL integration job role including Linting, CDC, manual integration, UPF, SDC, Synthesis, LEC and STA with multiple hands on projects.

📆Duration: 5 Months
🌐Mode: Online Live Sessions with Recorded Access
🧰Tools Covered: Synopsys TetraMax tools, MentorGraphics Tessent

Overview of the course

Hands-On Physical Verification Training with Industry Projects & EDA Tool Exposure

The 4-month Physical Verification Training at Vidyouth Intelligence is designed for freshers and experienced engineers aiming to specialize in backend VLSI roles. The program prepares students in all key aspects of Physical Verification including DRC, LVS, ERC, Antenna Checks, Latch-up, and reliability-focused checks like EM/IR, ESD, and DFM.

What You Will Learn

Physical Verification Fundamentals
Understand core concepts like DRCs, LVS, ERC, Antenna effects, Latch-up, and advanced checks such as EM/IR analysis and ESD path validation.

Layout Analysis and Design
Gain knowledge in standard cell, IO, memory, and analog layouts, including CMOS and FinFET design considerations.

ASIC Design Flow & Fabrication Process
Build a strong foundation in digital design flow, semiconductor basics, and manufacturing effects through real-world examples and projects.

Tool-Based Hands-On Projects
Over 70% of the course is dedicated to labs and projects using industry tools, ensuring practical exposure to physical verification flows.

Key Features
Balanced mix of 70% hands-on and 30% theory
20+ labs and multiple live projects for real-world experience
Training on UNIX, scripting, version control, and soft skills
Covers advanced layout topics and reliability checks in depth

Why Vidyouth Intelligence
Curriculum designed by VLSI professionals with real-time project insights
Live online classes combined with offline lab sessions
Comprehensive mentoring and personalized interview preparation
Tailored for B.Tech, M.Tech, BE, ME, diploma holders, and working professionals

This program ensures every learner is job-ready for the role of a Physical Verification Engineer, equipped with the technical knowledge, tool expertise, and confidence to excel in the semiconductor industry.

Course Syllabus

version control training
  • Revision Management
    • IBM Clearcase
    • GIT
  • Project Management
    • Detailed overview of project phases
    • Significance of RTL integration in VLSI Design Flow
RTL Integration
  • Overview of RTL Integration
  • Manual RTL integration
  • Need for Tool based Integration
  • CoreTools basics
  • Usage model for IP packaging
  • Usage model for IP integration
Linting
  • RTL Lint basics
  • Purpose of Linting
  • Rules in Spyglass Lint
  • Lint targets
  • Lint_rtl goal
  • Linting tools
  • Spyglass tool flow and setup
  • Rules in Spyglass lint
  • Typical Lint targets
  • Design read
  • Goal selection and setup
  • Run analysis and debug
  • Lint hands on example
Clock Domain Crossing
  • CDC basics
  • Clock domains and clock groups
  • Principles of Synchronous design
  • CDC synchronization techniques
  • CDC problems and solutions
  • Issues in CDC flow – Single bit crossing and multi bit crossing
  • CDC flow for burst data
  • Constraints versus Waivers
  • Capturing design intent using CDC constraints
  • Spyglass tool setup
  • Run analysis and debug
  • Abstract CDC flow
  • Hierarchical waiver in SoC CDC methodology
Power Aware Design Techniques - VCLP
  • Introduction to Low Power
  • Need for low power design
  • Understanding power intent
  • Types of power consumption
  • Power reduction techniques
  • Special cells for low power techniques
    • Power switches
    • Isolation cells
    • Level shifters
    • Always on logic
    • Retention registers
  • UPF
    • UPF commands
    • UPF flow
    • Power domains
    • Power state table
    • Retention strategies
    • Isolation strategies
    • Level shifting strategies
  • VCLP tool flow
    • Reading the design
    • Reading Power intent and running VCLP checks
    • VCLP run script
SDC - Synopsys design constraints
  • Importance of SDC
  • SDC basics
  • Defining clock
  • Defining interface timing
  • Defining exception
  • SDC implementation with hands on project
RTL Synthesis using Design compiler
  • Introduction to Synthesis
  • Data Setup for DC
  • Accessing Design and Library Objects
  • Constraints: Reg-to-Reg and I/O Timing
  • Constraints: Input Transition and Output Loading
  • Constraints: Multiple Clocks and Exceptions
  • Constraints: Complex Design Considerations
  • Post-Synthesis Output Data
Logic Equivalence Checks (LEC)
  • LEC basics
  • Need for LEC?
  • Logic Equivalence checks
  • Combinational Equivalence
  • Sequential Equivalence
  • Transaction Equivalence
  • Logic Equivalence checks
  • Setup mode
  • Mapping mode
  • Compare mode
  • Formal verification
  • FormalPro tool overview
  • Formality tool overview
  • Input files
  • Black box files
  • Constraint files
  • Debugging the failures
  • Hands on project
Static timing analysis
  • STA using Prime time flow
  • Fixing setup and hold time violations
  • Analyzing false and multi cycle paths

Course Highlights

  • 100% Placement Support 
  • Designed for Freshers
  • System Verilog, UVM, Protocols
  • Trainers from MNCs with 10+ Years’ Experience
  • Daily Class Recordings
  • 24×7 Support
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