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FPGA SYSTEM DESIGN TRAINING

FPGA System Design training is a 6 months course provides participants with wider and deep understanding of the FPGA Architecture, Design, Timing closure flow and debugging.

📆Duration: 7 Months
🌐Mode: Online Live Sessions with Recorded Access
🧰Tools Covered: Synopsys and Cadence Innovus  Tools.

Overview of the course

Comprehensive Functional Verification Training with Industry Tools, Protocols & Live Projects
The 8-month Functional Verification Course at Vidyouth Intelligence is designed to prepare freshers for front-end verification roles in the VLSI industry. It offers a perfect balance of conceptual training, hands-on practice, and real-time project exposure.

What You Will Learn

Core Verification Foundations
Gain proficiency in Verilog, SystemVerilog, UVM, and assertions, with practical implementation at the core.

Protocol and SoC-Level Knowledge
Learn key industry protocols like AXI, AHB, and APB, along with SoC-level verification and ASIC design flow.

Scripting and Automation
Master TCL and Python for efficient automation and enhanced productivity in verification environments.

Tool Proficiency
Get trained on industry tools like Synopsys VCS, Cadence Xcelium, and Mentor Questasim for real-world simulation experience.

Project-Based Learning
Work on IP-level and SoC-level projects under expert guidance, gaining end-to-end exposure to verification flow.

Key Features
Structured, industry-aligned curriculum with 40+ assignments and continuous assessments
Real-time labs, examples, and verification challenges for hands-on learning
Daily session recordings for easy revision and flexible learning
Weekly evaluations and continuous mentoring by VLSI professionals

Why Vidyouth Intelligence
Program designed and taught by industry experts from top semiconductor firms
Hybrid learning model with online theory and offline lab sessions
Individualized mentoring and strong placement assistance with written guarantee
Affordable and outcome-driven, ideal for ECE, EEE, and related engineering graduates

The Functional Verification Program ensures students enter the VLSI field with confidence, technical expertise, and job-ready skills.

Course Syllabus

ASIC Flow
  • Specification
  • RTL coding, lint checks
  • RTL integration
  • Connectivity checks
  • Functional Verification
  • Synthesis & STA
  • Gate level simulations
  • Power aware simulations
  • Placement and Routing
  • DFT
  • Custom layout
  • Post silicon validation
Digital Design - Deep dive
  • Combinational logic
    • Number systems
    • Radix conversions
    • K-maps, min-terms, max terms
    • Logic gates
    • Realization of logic gates using mux’s and universal gates
    • Compliments (1/2/9/10’s complement)
    • Arithmetic operations using compliments
    • Boolean expression minimization, Dmorgan theorems
    • POS and SOP
    • Conversion and realization
    • Adders
      • Half adder
      • Full adder
    • Subtractor
      • Half subtractor
      • Full subtractor
    • Multiplexers
    • Realizing bigger Mux’s using smaller Mux’s
    • Implementing Adders and subtractors using Multiplexers
    • Decoders and Encoders
    • Implementing Decoders and Encoders using Mux and Demux
    • Bigger Decoder/Encoder using smaller Decoder/Encoder
    • Comparators
    • Implementing multi bit Comparators using 1-bit Comparator
  • Sequential logic
    • Latch, Flipflop
    • Latch, Flipflop using Gates or Mux’s
    • Different types of FFs
    • FF Truth table
    • Excitation tables
    • Realization of FF’s using other FF’s
    • Applications of FF’s, Latches
      • Counters
      • Shift registers
      • Synchronizers for clock domain crossing
      • FSM’s
      • Mealy, Moore FSM
      • Different encoding styles
      • Frequency dividers
      • Frequency multiplication
    • STA
      • Setup time, Hold time, timing closure
      • fixing setup time and hold time violations
      • Launch flop, capture flop
SOC Design and Verification concepts
  • SOC Architecture overview
  • SOC design concepts
  • SOC verification concepts
  • SOC Components
  • SOC use cases
  • SOC Testbench architecture
  • SOC Test Case coding
  • SOC verification differences with module verification
Linux commands - hands on training
  • Installing Linux platform in Windows
  • Linux basics
  • Linux versus Windows
  • Linux Terminal
  • File and Directory management
  • Changing file permissions
  • Absolute path and relative path
  • Working with directories
  • GVIM – major keyboard shortcuts
  • Text display commands
  • Root configuration files
  • Environment variables
  • Text processing commands
  • Connecting to server
  • Process management
  • LSF
  • Ping
  • FTP
  • CTAGs
  • File compress and extract
  • Softlinks
Verilog language - Deep dive
  • Verilog language basics
  • Verilog : How the language evolved?
  • Verilog execution using Modelsim
  • Verilog constructs       
          
  • Literals
  • Data types
  • Operators
  • Continuous assignments
  • Procedural timing controls
  • task and functions
  • system task and function
  • modeling memories and FSM
  • Parameters
  • Port connections
  • Procedural blocks
  • Sensitivity list
  • State machines
  • timescale
  • Verilog timing regions
  • process
  • Blocking and nonblocking statements
  • Inferring combinational and Sequential logic
  • fork join
  • Race conditions
  • Synthesis examples
  • Inter and Intra delay statements
  • Pipelining
  • PLI
  • compiler directives
Verilog design and verification projects

    • 1. Flip-Flops (DFF)

      • DFF Coding using Gate-Level Modeling

      • DFF Coding using Behavioral Modeling

      2. Counters

      • Up Counter

      • Ring Counter

      • Johnson Counter

      3. Finite State Machines (FSM)

      • Mealy Style FSM (Implicit and Explicit Coding)

      • Moore Style FSM (Implicit and Explicit Coding)

      4. Pattern Detectors

      • Overlapping Pattern Detector

      • Non-Overlapping Pattern Detector

      • Dynamic Pattern Detector

      5. Memory Design and Verification

      • Memory Verilog Coding

      • Front Door Access

      • Back Door Access

      • Test Case Coding and Waveform Analysis

      6. FIFO (First-In First-Out) Design

      • Synchronous FIFO

      • Asynchronous FIFO

      7. Controllers and Protocols

      • Traffic Light Controller

      • APB Protocol Implementation

      • Interrupt Controller

      • SPI (Serial Peripheral Interface) Controller

      8. Error Detection

      • CRC (Cyclic Redundancy Check) Generation

FPGA Design and FPGA design Flow
  • PAL, CPLD and FPGA basics
  • FPGA Design Flow
FPGA Architecture
  • Internals of FPGA and CPLD
  • Logic implementation
  • FPGA Architectures of various FPGA vendors
  • Anti-fuse and SRAMS
  • Logic elements and Look-up Tables
  • Dedicated multipliers
  • Distributed RAM
  • Shift registers
  • MMCM
  • Kintex
  • Zynq
  • Virtex Architectures
IP Cores
  • Introduction and usage of IP cores·
FPGA Simulation and Synthesis Tool Flow
  • Modelsim/Icarus Verilog simulation
  • Design Synthesis
FPGA Implementation Design Flow
  • Design constraining and pin locking
    • Timing analysis
    • slack calculation
    • Data loss due to large skew
    • Maximum skew calculations with examples
    • Period constraints
    • Area and Power Constraints
  • Static Timing Analysis
  • FPGA programming
  • Translate
  • Map
  • Floor plan
  • Place and Route
  • Post map and Post P&R simulation
  • XDC constraints
  • Reading and analysing reports-post synthesis
  • Post map simulation
  • Post P·&R simulation
  • Configuring FPGAs
  • FSM Extraction
Timing Simulation and Programming
  • Timing Simulation using Modelsim/Icarusverilog
  • Programming using JTAG
System Level testing and debugging
  • Debugging techniques
    • Debugging using chip scope and Logic analyzers
    • Protocols on FPGA
    • High Speed SERDES
  • Identification of the issues/resolving
FPGA SDK environment
  • FPGA SDK environment
  • FPGA Device selection 
PERL/Python Scripting
  • PERL Interpreter
  • Variables
  • File management
  • Subroutines
  • Regular expressions
  • Object oriented PERL
  • PERL modules
Soft Skill Training
  • Facing interviews effectively
  • industry work culture
  • Group discussions
Course Assignments
  • 100+ detailed assignments covering all aspects from VLSI Flow, SOC Design, Verilog, Advanced digital design, System verilog, AXI protocol, VIP Development, RTL debug, UNIX and PERL scripting.

Course Highlights

  • 100% Placement Support
  • Designed for Freshers
  • System Verilog, UVM, Protocols
  • Trainers from MNCs with 10+ Years’ Experience
  • Daily Class Recordings
  • 24×7 Support
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