• Verilog language basics
• Verilog : How the language evolved?
• Verilog execution using Modelsim
• Verilog constructs
• Literals
• Data types
• registers, nets
• Vectors, Array
• Operators
• Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
• Continuous assignments
• Combinational logic coding : Half adder, full adder, multiplexer, comparator, encoder, decoder, priority encoder
• Generate
• Procedural timing controls
• task and functions
• system task and function
• modeling memories and FSM
• Parameters
• Port connections
• Procedural blocks
• Sensitivity list
• State machines
• timescale
• Verilog timing regions
• process
• Blocking and nonblocking statements
• Inferring combinational and Sequential logic
• Clock generation with Duty cycle & Jitter
• Shift register implementation
• Procedural Blocks
• fork join
• Race conditions
• Synthesis examples
• Inter and Intra delay statements
• example to showcase race condition using blocking assignments
• Pipelining
• Memories
• Structural modeling
• Verilog Programming Interface(& PLI)
• PLI
• compiler directives
• system task usage: $display, $monitor, $strobe
• PLI, VPI implementation
• Primitive implementation using table, endtable

• DFF coding using gate level, behavioral
• Counters
• Up counter
• Ring counter
• Johnson counter
• Memory RTL coding and TB development
• Memory Verilog coding
• Declaring a parameterized memory
• Front door access
• Back door access test case coding
• Implemneting task for front door and back door access
• Test case coding and understanding waveforms
• FIFO – Synchronous FIFO and Asynchronous FIFO
• Synchronous FIFO
• Asynchronous FIFO
• Finite state machines
• Mealy and Moore style
• Implicit and Explicit styles of coding.
• Pattern detector – Overlapping, Non-Overlapping, Dynamic
• Overlapping
• Non-Overlapping
• Dynamic
• Traffic light controller
• APB protocol
• Interrupt controller
• SPI controller
• CRC generation

Sample text

• What is UVM? Need for a methodology?
• How UVM evolved?
  • OVM, AVM, RVM, NVM, eRM
• UVM class library
  • Classification of base classes in various categories
• OOP basics
  • Encapsulation
  • Inheritance
  • Polymorphism
  • Parameterized classes
  • Parameterized macros
  • Static properties and static methods
  • Abstract classes
    • Pure virtual methods
  • How above aspect correlates with UVM implementation.
• UVM Class Library, Macros, Utilities
  • Detailed overview of important UVM base classes, Macros and Utility classes.
• UVM TB Architecture
  • Setting up a UVM based testbench for APB protocol from scratch.
  • Significance of uvm_root in UVM based testbenches.
    • run_test, how it starts whole TB flow.
• Command line processor
• Reporting classes
  • Uvm_report_object
  • Uvm_report_handler
  • Uvm_report_server
  • Detailed examples on use of methods in these classes.
• Objections
• UVM Factory
• Configuration DB, Resource DB
  • Detailed usage of both data bases.
  • How config_db is related to resource_db?
  • Using config_db to change the testbench architecture.
• TLM1.0
  • Push
  • Pull
  • FIFO
  • Analysis
  • Complex example on AHB to AXI transaction conversion.
• Simulation Phases
  • UVM common phases
  • Scheduled phases
• Sequences, Sequencers
  • Default sequence
  • p_sequencer
  • m_sequencer
• Test case development
  • Different styles of mapping testcase to sequence
    • Using default sequence and scheduled phases
    • Using sequence start method
• Configuring TB Environment
  • Advanced aspects of developing a highly configurable test bench environment.
  • Concept of knobs of test case scenario generation
  • Using top level parameters to control the overall TB architecture
• Different testbench component coding
  • Monitor
  • Coverage
  • Scoreboard
  • Checkers
  • Assertions
• Different styles of sequence development
  • `uvm_do
  • Start_item and finish_item
  • Using existing sequences
• Sequence library
  • Creating complex test cases using sequence library
• Virtual Sequencer, Virtual sequences

• Installing Linux platform in Windows
• Linux basics
• Linux versus Windows
• Linux Terminal
• File and Directory management
• Changing file permissions
• Absolute path and relative path
• Working with directories
• GVIM – major keyboard shortcuts
• Text display commands
• Root configuration files
• Environment variables
• Text processing commands
• grep, fgrep
• xargs
• SEd
• AWK
• Pipes and filters
• Connecting to server
• Process management
• LSF
• Ping
• FTP
• CTAGs
• File compress and extract
• Soft links

• Protocol basics
  • Protocol overview
  • Protocol features
  • AMBA protocol overview
  • AXI Protocol basics
• SOC Architecture – Significance of AXI protocol
• AXI based system architecture
• Correlating AXI with APB protocol
  • Ports(signals) required for AXI protocol
• AXI Channels
  • Write & Read Channels
  • Handshaking using valid and ready
  • Write Channel Signals – Address, Data and Response
  • Read Channel Signals – Address and Data
• Timing diagrams
  • How to draw the timing diagrams?
  • Write Transaction Timing Diagram
  • Read Transaction Timing Diagram
• AXI transaction analysis for big endian and little endian architecture
• Wrap transactions – write and read
• Narrow transfers
• Data bus and strobe relation
• Aligned and unaligned transfers
• AXI signal encoding
• Responses in AXI
• Locked and exclusive transfers
• Overlapping, out of order, interleaved txs
• Interconnect role in out of order transaction
• Significance of ID in AXI protocol
• AXI Channel handshake dependency
• Cacheable and bufferable transactions
• Protected transactions
• AXI VIP and UVC development
  • Need for UVC?
  • Different types of UVC’s
  • UVC usage in module and SOC verification
  • Where Passive UVC are used?
  • UVC integration in to TB
  • AXI UVC architecture
  • AXI Transaction Definition
  • AXI UVC coding
  • AXI TB simulation and wave form analysis
  • AXI UVC integration
  • AXI scoreboard coding

• SoC Verification Concepts
• Module Level Verification
• Constrained Random Verification
• Coverage Driven Verification
• Directed Verification
• Assertion Based Verification

• Reading design specification
• How to read specification – understanding architecture, sub blocks, interfaces, registers
• Listing down features, scenarios
• Develop testplan
• Functional coverage point list down
• Develop Testbench architecture
• Testbench component coding and integration
• Develop sanity testcases(smoke tests)
• Bring up test bench environment using sanity testcases
• Develop rest of test bench components including monitor, coverage and scoreboard
• Register model(RAL) development and integration
• Register write-read, reset tests using front door and back door access
• Functional testcase coding using Register model
• Functional testcase debug using RTL, data flow and schematic tracing
• Setup regression using Python
• Debug regression failures
• Functional, Code and assertion coverage analysis
• Develop more functional tests for coverage improvement

• Schematic tracing
• RTL tracing
• FIxing RTL and TB syntax and logical errors

• SOC Architecture overview
• SOC verification concepts
• SOC Components
• SOC use cases
• SOC Testbench architecture
• SOC verification differences with module verification

• Specification
• RTL coding, lint checks
• RTL integration
• Connectivity checks
• Functional Verification
• Synthesis & STA
• Gate level simulations
• Power aware simulations
• Placement and Routing
• DFT
• Custom layout
• Post silicon validation

• Python Interpreter
• Variables
• File management
• Subroutines
• Regular expressions
• Object oriented Python
• Python modules

• Facing interviews effectively
• industry work culture
• Group discussions

100+ detailed assignments covering all aspects from Verilog, Advanced digital design, System verilog, UVM, AXI protocol, VIP Development, Ethernet MAC core verification, RTL debug, UNIX and PERL scripting.