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PHYSICAL VERIFICATION TRAINING

Physical Verification training is a four months course targeted for experienced engineers, BTech, BE, MTech, ME and diploma graduates planning to make career as a Physical verification engineer.

📆Duration: 5 Months
🌐Mode: Online Live Sessions with Recorded Access
🧰Tools Covered: Synopsys TetraMax tools, MentorGraphics Tessent 

Overview of the course

Hands-On Physical Verification Training with Industry Projects & EDA Tool Exposure

The 4-month Physical Verification Training at Vidyouth Intelligence is designed for freshers and experienced engineers aiming to specialize in backend VLSI roles. The program prepares students in all key aspects of Physical Verification including DRC, LVS, ERC, Antenna Checks, Latch-up, and reliability-focused checks like EM/IR, ESD, and DFM.

What You Will Learn

Physical Verification Fundamentals
Understand core concepts like DRCs, LVS, ERC, Antenna effects, Latch-up, and advanced checks such as EM/IR analysis and ESD path validation.

Layout Analysis and Design
Gain knowledge in standard cell, IO, memory, and analog layouts, including CMOS and FinFET design considerations.

ASIC Design Flow & Fabrication Process
Build a strong foundation in digital design flow, semiconductor basics, and manufacturing effects through real-world examples and projects.

Tool-Based Hands-On Projects
Over 70% of the course is dedicated to labs and projects using industry tools, ensuring practical exposure to physical verification flows.

Key Features
Balanced mix of 70% hands-on and 30% theory
20+ labs and multiple live projects for real-world experience
Training on UNIX, scripting, version control, and soft skills
Covers advanced layout topics and reliability checks in depth

Why Vidyouth Intelligence
Curriculum designed by VLSI professionals with real-time project insights
Live online classes combined with offline lab sessions
Comprehensive mentoring and personalized interview preparation
Tailored for B.Tech, M.Tech, BE, ME, diploma holders, and working professionals

This program ensures every learner is job-ready for the role of a Physical Verification Engineer, equipped with the technical knowledge, tool expertise, and confidence to excel in the semiconductor industry.

Course Syllabus

ASIC Flow Overview
  • Requirements
  • Design specification & architecture
  • RTL Coding
  • RTL integration
  • Functional verification
  • Synthesis
  • DFT
  • Physical Design
  • STA
  • Custom Layout
  • Physical Verification
  • Post Silicon Validation
Advanced Digital Design
  1. Digital Design syllabus
Essentials of UNIX/Linux
    1. Linux/UNIX OS, Shell
    2. Working with files, directories
    3. Commonly used commands
Semiconductor Basics
  • Conductor, Semiconductor & Insulators -> Intrinsic & Extrinsic Semiconductor.
  • Basic Passive and Active devices.
  • Ohms law, Kirchoff laws
  • Basic of circuit understandin
CMOS & FINFET Basics
  • MOSFET Basics, Operations, few simple circuits & second order effects.
  • MOSFET Detailed fabrication process.
  • FinFET working, Fabrication, advantages & disadvantages.
Moderated Group Discussion
  • Group discussions will be running throughout the course 
Layout tool
  • Layout Editor Tool
  • Understanding the schematic symbols and parameters
  • Creating and managing libraries and cell
  • Commands for Layout editing.
  • Commands for schematic editing.
  • Verification : DRC and LVS
  • Antenna effect, latchup, Electromigration, IR Drop
  • Analog Layout of OpAmp, Current Mirror, PLL, ADC, and DAC
  • Resistor, Capacitor layout techniques
  • CMOS and BiCMOS layout techniques
  • Standard Cell Layout : Inverter, AND, OR, NAND, NOR, AOI, OAI, Latches, and Flop
Physical Verification Concepts
  • Design Rule Checks
  • Layout Versus Schematic (LVS)
  • Electrical Rule Checks (ERC)
  • Antenna Checks
  • Latch-up
  • Reliability checks like EM and IR analysis
  • Design for manufacturability (DFM)checks
  • Electrostatic discharge (ESD) path checks
Physical Verification Hands on projects
  • Multiple projects with detailed Physical verification analysis
Assignments and hands on projects
  • Assignments and multiple hands on projects
  • Best Practices & Interview Questions. 

Course Highlights

  • 100% Placement Support  
  • Designed for Freshers
  • System Verilog, UVM, Protocols
  • Trainers from MNCs with 10+ Years’ Experience
  • Daily Class Recordings
  • 24×7 Support
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